1. Field of the invention
The present invention relates to a method and apparatus for forming copper wiring, and more particularly to a method and apparatus for forming copper wiring on a substrate such as a semiconductor wafer.
2. Description of the Related Art
Conventionally, in order to form a wiring circuit on a semiconductor substrate, a conductive film is deposited over a surface of a substrate by a sputtering process or the like, and then unnecessary portions are removed from the conductive film by a chemical dry etching process using a photoresist for a mask pattern.
Generally, aluminum or aluminum alloy has been used as a material for forming a wiring circuit. However, the higher integration of integrated circuits on the semiconductor substrate in recent years requires narrower wiring to thus increase the current density, resulting in generation of thermal stress in the wiring and increase in the temperature of the wiring. This unfavorable condition becomes more significant, as wiring material such as aluminum is thinner due to stress-migration or electromigration, to finally cause a breaking of the wire or a short circuit.
Hence, in order to prevent the wiring from generating excess heat while current flows, a material such as copper having a higher electrical conductivity is required to be used for a wiring circuit. However, since copper or copper alloy is not suited for the dry etching process, it is difficult to adopt the above-mentioned method in which the wiring pattern is formed after depositing the conductive film over the whole surface of the substrate. Therefore, one possible process is to form grooves for a wiring circuit having a predetermined pattern, and then fill the grooves with copper or copper alloy. This process eliminates the etching process of removing unnecessary portions of the film, and needs only a polishing process of removing unevenness or irregularities of the surface. Further, this process offers advantages that portions called wiring holes connecting between an upper layer and a lower layer in a multilayer circuit can be formed at the same time.
However, as the width of wiring becomes narrower, such wiring grooves or wiring holes have a considerably higher aspect ratio (the ratio of depth to diameter or width), and hence it is difficult to fill the grooves or the holes with metal uniformly by the sputtering process. Further, although a chemical vapor deposition (CVD) process is used to deposit various materials, it is difficult to prepare an appropriate gas material for copper or copper alloy, and if an organic material is used for depositing copper or copper alloy, carbon (C) is mixed into a deposited film to increase migration of the film.
Therefore, there has been proposed a method in which a substrate is dipped in a plating solution to plate the substrate with copper by an electrolytic plating or an electroless plating, and then the unnecessary portion of a copper layer is removed from the substrate by a chemical mechanical polishing (CMP) process. This formation of the film or layer by the plating allows wiring grooves having a high aspect ratio to be uniformly filled with a metal having a high electrical conductivity. In the CMP process, a semiconductor wafer held by the top ring is pressed against a polishing cloth attached to a turntable, while supplying a polishing liquid containing abrasive particles and thus the copper layer on the semiconductor substrate is polished.
However, in the CMP process described above, the pattern density dependence on the properties of the polishing cloth and the polishing liquid is large, and copper wiring portions are excessively polished in the form of a plate or a dish. This excessively polished phenomenon is called "dishing".